Personal computers and other computing systems generally include a central processing unit (CPU) operating under control of an operating system and/or other software. Peripheral devices are generally connected to the CPU via one or more busses. In order to notify the CPU and/or the operating system of a pending task, the peripheral devices are typically configured to issue interrupts. In order to controllably direct the interrupts to the CPU, a personal computer or other computing system may include an interrupt handler, such as a Programmable Interrupt Controller (PIC), that receives the interrupts from the peripheral devices and issues an appropriate interrupt signal to the CPU. As such, the interrupt handler effectively serves to multiplex the interrupts from the peripheral devices for presentation to the CPU. The CPU, in turn, responds to the interrupt and interacts with the peripheral device issuing the interrupt to perform the desired task or the like.
For personal computers, peripheral devices are oftentimes connected to a Peripheral Component Interconnect (PCI) bus. The PCI bus is, in turn, connected via a PCI bridge to a host bus which serves to interconnect the CPU and the main memory associated with the CPU. The PCI bus generally includes a number of slots for receiving respective peripheral devices, i.e., peripheral devices may be plugged into respective slots. While a variety of peripheral devices may be connected to the PCI bus via respective slots, typical examples include a graphics adapter, a Small Computer Systems Interface (SCSI) host adapter, a local area network (LAN) adapter, an input/output (I/O) unit and an audio and motion video unit.
The slots of a PCI bus are generally capable of issuing four IRQs, typically designed as INTA, INTB, INTC and INTD. The interrupts generated by each slot are directed to a PCI interrupt router, hereinafter referenced as a PCI router, which, in turn, issues an appropriate signal to the interrupt handler for notifying the CPU of the pending interrupt. In embodiments in which the interrupt handler is a PIC, for example, the PCI router will direct the interrupt to the PIC via a PIC bus that extends between the PCI router and the interrupt handler.
A PCI router generally includes a plurality of links, such as four links designated LNKA, LNKB, LNKC and LNKD, for receiving IRQs. In this regard, the interrupts issued by the devices inserted into respective slots of the PCI bus are connected to respective links and are therefore directed to the PCI router. Upon receipt of an interrupt via one of the links, the PCI router issues a signal to the interrupt handler which, in turn, notifies the CPU. An interrupt handler generally includes a plurality of IRQ inputs, such as sixteen IRQ inputs designated IRQO, IRQ1, . . . IRQ15. The PCI router may therefore be connected to one or more of the IRQ inputs of the interrupt handler, such as via the PIC bus or the like. For example, a PCI router may be connected to four of the IRQ inputs of an interrupt handler such that interrupts provided to the PCI router via LNKA cause an interrupt request to be asserted via a first IRQ input, interrupts provided to the PCI router via LNKB cause an interrupt request to be asserted via a second IRQ input and so on. The interrupt handler will then provide an appropriate IRQ to the CPU which, in turn, will attend to the task that originally triggered the interrupt.
Initially, the interrupts generated by the devices inserted into each slot of a PCI bus were connected to the links of the PCI router in the same fashion. In this regard, INTA of each slot was typically connected to LNKA, INTB of each slot was connected to LNKB, INTC of each slot was connected to LNKC and INTD of each slot was connected to LNKD. Since the interrupts generated by each slot were connected to the links of the PCI router in the same manner, it was difficult to identify the peripheral device that generated an interrupt. Thus, upon receiving an interrupt request, each peripheral device generally had to be polled to determine which peripheral device had generated the interrupt. In this regard, each peripheral device could include a status register that could be set to a predefined value upon the issuance of an interrupt. As such, in polling the peripheral devices, the status register of each peripheral device could be examined to determine if the peripheral device had issued the interrupt. As will be apparent, this process of polling the peripheral devices to determine which peripheral device had generated the interrupt may be somewhat time-consuming and delay the handling of the interrupt.
In order to permit the peripheral device that issued an interrupt to be identified in a more efficient manner, the interrupts generated by the respective slots of a PCI bus have been connected to the links of the PCI router in a round-robin fashion. In this regard, the interrupts generated by different slots of the PCI bus were connected to the links of the PCI router in different manners. In a round-robin configuration, the interrupts of the first slot of the PCI bus are connected such that INTA is connected to LNKA, INTB is connected to LNKB, INTC is connected to LNKC and INTD is connected to LNKD. Further, the interrupts of the second slot of the PCI bus are connected such that INTA is connected to LNKB, INTB is connected to LNKC, INTC is connected to LNKD and INTD is connected to LNKA. Similarly, the interrupts of the third slot of the PCI bus are connected to the links of the PCI router such that INTA is connected to LNKC, INTB is connected to LNKD, INTC is connected to LNKA and INTD is connected to LNKB. Finally, the interrupts of a fourth PCI slot would be connected such that INTA is connected to LNKD, INTB is connected to LNKA, INTC is connected to LNKB and INTD is connected to LNKC. Since interrupts are most frequently issued via INTA, the peripheral device that issued an interrupt may be more expeditiously determined by polling the peripheral device having INTA connected to the respective link of the PCI router which reported the interrupt. If the peripheral device having INTA connected to the respective link of the PCI router did not issue the interrupt, the other peripheral devices may then be polled.
In many instances, however, the PCI bus has more than four slots. In a round robin configuration, the interrupts of the fifth slot are generally connected to the links of the PCI router in the same manner as the interrupts of the first slot. Similarly, the interrupts of the sixth slot are generally connected in the same fashion as the interrupts of the second slot, and so forth. Additionally, other techniques for routing the interrupts of the various devices via the links to the PCI router have also been utilized. Each of these routing techniques generally required some time to be expended in order to identify the peripheral device that issued the interrupt and to thereafter respond to the interrupt.
In order to provide the operating system with information defining the routing or configuration of the IRQs so that interrupts can be handled more efficiently, IRQ routing tables have been constructed. Among other things, IRQ routing tables identify the IRQ input of the interrupt handler to which the different links of the PCI router are connected. By referring to the IRQ routing table in response to an interrupt request, the operating system can determine the link of the PCI router that provided the interrupt. By polling the peripheral devices having interrupts connected to the respective link of the PCI router and, in particular, the peripheral devices having INTA connected to the respective link of the PCI router, the operating system can more quickly determine the source of the interrupt.
Since interrupts are frequently configured or routed in different manners, such as by being connected in different sequences to the respective links of a PCI router, the IRQ routing table must generally be manually constructed. In this regard, the computers sold by different manufacturers may require different IRQ routing tables depending upon the configuration or routing of the interrupts. Likewise, different models of computers sold by the same manufacturer may require different IRQ routing tables.
Depending upon the computer, additional routing tables and/or other types of routing information may be created based upon the IRQ routing table for use by the operating system. In this regard, a PCI BIOS IRQ routing table may be constructed for use by the basic input/output system (BIOS). Additionally, a Microsoft IRQ routing table may be constructed for use by various Microsoft operating systems. Advanced Configuration and Power Interface (ACPI) IRQ routing information and/or multiprocessor (MP) IRQ routing information may be constructed. Finally, at least a portion of the data contained by the IRQ routing table may be included within the system management BIOS (SMBIOS).
As will be apparent, the manual construction of an IRQ routing table can be relatively complex and typically requires a skilled designer having experience with interrupt routing and the manner in which different configurations or routes for interrupts are reflected in an IRQ routing table. As a result of the manual construction of the IRQ routing table, it is also possible for errors to be inadvertently introduced into the IRQ routing table as well as the other routing tables and routing information created therefrom, thereby potentially creating substantial problems in interrupt handling. As such, it would be advantageous to provide an improved technique for configuring or routing interrupts from the various peripheral devices and for generating IRQ routing tables and other types of routing information in a more efficient and accurate manner.